Since carbon nanotubes have good electrical characteristics, the application of carbon nanotubes to the wiring of semiconductor devices and the like has been being examined. As for a method for forming a carbon nanotube film, there is suggested in, e.g., Japanese Patent Application Publication No. 2007-252970, a method for forming carbon nanotubes by forming a catalyst layer made of particles of a transition metal such as Ni, Fe, Co or the like on a substrate and performing thereon plasma CVD using hydrocarbon gas and hydrogen gas. The above-cited reference discloses a technique for activating a surface of a catalyst metal by allowing radicals to act on the surface of the catalyst metal for the purpose of preventing catalyst activation from being deteriorated by oxidation of the surfaces of fine particles when the catalyst metal is atomized.
In order to use carbon nanotubes for via wirings, it is required to reduce defects of the carbon nanotubes and increase the density per unit area. When the density of the carbon nanotubes filled in the openings are low, the following problems are generated. First, fine gaps are formed in the openings and, thus, the conductivity of the via wiring is decreased. Further, when the planarization is performed by, e.g., CMP (chemical mechanical polishing) after the carbon nanotubes are filled in the openings, the carbon nanotubes filled in the openings are separated therefrom. Moreover, when fine gaps are formed in the openings after the carbon nanotubes are filled, the fine gaps need to be filled with, e.g., silicon dioxide films or the like. Hence, the number of processes is increased and the processes are not efficiently performed in view of an industrial scale.
In Japanese Patent Application Publication No. 2007-252970, only the case of forming a carbon nanotube film on a flat surface is disclosed. Therefore, simply by activating a catalyst metal, it is difficult to fill carbon nanotubes in openings such as via holes and the like with a high density.